1. Field of the Invention
The present invention relates to a semiconductor device used as a high-speed switching device and a power device, for example, a lateral MOS field effect transistor (hereinafter referred to as a lateral MOSFET).
2. Description of the Related Art
In recent years, development of lateral MOSFETs (LDMOSs) has advanced (see, for example, Jpn. PCT National Publication No. 2004-516652). For the purpose of a high-speed operation, it is required to reduce the capacitance between a gate and a drain, and a structure that satisfies the requirement has been considered. More specifically, the following measures have been considered: (1) to reduce the overlap between a gate and a resurf layer; (2) to make the conductivity type of a region under a gate opposite to that of a drain (for example, in the case of an N-channel MOSFET, a P-type region is formed under the gate); and (3) to shorten the gate length.
When the structure is employed, in which the overlap between a gate and a drain is minimized in order to reduce the gate length and to reduce the capacitance between a gate and a drain, the following problems arise in forming a channel region.
In general, in the case of a CMOS structure, ion implantation (channel ion implantation) is performed on the overall semiconductor region surface, that is, in both source and drain regions, in order to form a channel region to control a threshold voltage. Thus, the channel concentration in a region under a gate is substantially uniform. In contrast, a lateral MOSFET has a so-called resurf region between a channel region and a drain region to keep the breakdown voltage high. The resurf region on the drain side has a lower impurity concentration and a longer length as compared to a lightly doped diffusion region (LDD) on the source side. Therefore, in the lateral MOSFET, if channel ion implantation is performed on the overall semiconductor region surface, that is, in both source and drain regions, as in the case of a CMOS, the device characteristics may be adversely affected. For example, the effective concentration of a resurf region may be lowered, or the drain region and the channel region form a pn junction portion at a high concentration. Further, if channel ion implantation is selectively performed by using a mask so that impurity ions are not implanted in the resurf region by the channel ion implantation, the displacement of the mask may significantly influence variations of the device characteristics.